This invention relates to the field of computer networks. In particular, the present invention provides a system and method for modulating or suppressing the issuance of interrupts from a communication device such as a network interface circuit (NIC).
The interface between a computer and a network is often a bottleneck for communications passing between the computer and the network. While computer performance (e.g., processor speed) has increased exponentially over the years and computer network transmission speeds have undergone similar increases, inefficiencies in the way network interface circuits handle communications have become more and more evident. With each incremental increase in computer or network speed, it becomes ever more apparent that the interface between the computer and the network cannot keep pace. These inefficiencies involve several basic problems in the way communications between a network and a computer are handled. Similar inefficiencies exist in other communication devices and conduits, including network devices such as routers, gateways, switches and input/output devices such as media (e.g., disk drive) controllers.
Today""s most popular forms of networks tend to be packet-based. These types of networks, including the Internet and many local area networks, transmit information in the form of packets. Each packet is separately created and transmitted by an originating endstation and is separately received and processed by a destination endstation. In addition, each packet may, in a bus topology network for example, be received and processed by numerous stations located between the originating and destination endstations.
One basic problem with packet networks is that it may take many packets to communicate a given amount of data from one endstation to another. When data transmitted between stations is longer than a certain minimal length, the data is divided into multiple portions, and each portion is carried by a separate packet. The amount of data that a packet can carry may be limited by the network that conveys the packet and is often expressed as a maximum transfer unit (MTU). The original aggregation of data is sometimes known as a xe2x80x9cdatagram,xe2x80x9d and each packet carrying part of a single datagram may be processed very similarly to the other packets of the datagram.
As the amount of data to be transmitted increases, the number of packets that must be sent to, and processed by, a destination endstation increase as well. Naturally, the more packets that must be processed, the greater the demand placed upon an endstation""s processor and the network interface serving that endstation. The number of packets that must be processed is affected by factors other than just the amount of data being sent in a datagram. For example, as the amount of data encapsulated in a packet increases, fewer packets need to be sent. As stated above, however, a packet may have a maximum allowable size, depending on the type of network in use (e.g., the maximum transfer unit for standard Ethernet traffic is approximately 1,500 bytes). The speed of the network also affects the number of packets that a NIC may handle in a given period of time. For example, a gigabit Ethernet network operating at a peak rate may require a NIC to receive approximately 1.48 million packets per second. Thus, the number of packets to be processed may place a significant burden upon a computer""s processor. The situation is exacerbated by the need to process each packet separately even though each one will be processed in a substantially similar manner.
Another obstacle to the efficient interaction of network interface circuits and host computers or other communication devices arises from the decreased host processor utilization that results when a network interface circuit issues numerous interrupts. In particular, in many present network interface circuits an interrupt may be issued to a host processor for each packet transferred to a host computer from a network. As the rate of network traffic increases, the rate of interrupt generation increases commensurately. The more packets that arrive at a network interface circuit, therefore, the more time the processor must spend on context switches and processing the interrupt, and the lower the effective utilization of the processor.
As the performance of a network interface circuit increases and packets are transferred to a host processor at a faster and faster rate, the rate of interrupt generation may approach a level that, given the time necessary for the processor to process an interrupt, monopolizes processor utilization. In fortuitous circumstances a processor may be able to process multiple packets during one interrupt service routine, but this may be offset by the high rate of packet arrival. Without a mechanism for suppressing or modulating the rate at which interrupts are generated from a network interface, a network interface capable of high performance may overwhelm a host processor. The rate of arrival of packets at a network interface circuit may become so high that the processor must spend an inordinate amount of time just servicing the interrupts and processing the packets received in between interrupts, thus severely diminishing its ability to perform other tasks.
Another method by which a host processor may learn of the receipt of network traffic is polling. An endstation may, for example, poll a network interface circuit to determine if there are any packets to be processed. Polling is inefficient, however, unless the level of network traffic is relatively high. In addition, if polling should be blocked or otherwise become unable to continue operation in existing implementations, network traffic may be brought to a standstill.
Thus, present methods of alerting host processors to the receipt of network traffic often fail to provide adequate performance to interconnect today""s high-end computer systems and high-speed networks. A network interface circuit that cannot make allowance for an over-burdened host computer may seriously degrade the computer""s performance. In particular, the use of interrupts may degrade a host processor""s performance during a high level of traffic, and polling may be unsuitable for lower levels of traffic.
In one embodiment of the invention, a system and method for polling a network interface are provided. In this embodiment an interrupt that would normally alert a host processor to the arrival of a network packet is suspended during a polling mode of operation. Each time the network interface is polled, any waiting packets are processed. However, if a threshold amount of time passes, or a threshold number of packets are received without being processed, interrupts may be enabled to ensure the packets are serviced. Thus, a polling mode of operation may be combined with interrupt modulation in one embodiment of the invention.
A network interface receives packets from a network for transfer to a host computer. Prior to the commencement of polling, when a packet is received by the network interface and transferred to the host computer an interrupt may be generated to alert a host processor. However, processing interrupts may cause significant overhead for the processor depending upon the level of traffic received at the network interface. Therefore, one or more embodiments of the present invention are configured to decrease the number of interrupts generated in response to the transfer of network packets without preventing the packets from being processed in a timely manner. More specifically, the generation of interrupts is suspended during a polling mode of operation. Each time the network interface is polled, received packets may be processed without having to wait for an interrupt. Thus, in one embodiment of the invention no interrupts are generated during a polling mode of operation.
If polling should fail or be blocked, however, the generation of interrupts may be re-enabled. The rate at which interrupts may then be issued to the host computer may be modulated in order to ensure that the host computer has time to perform other functions. In particular, in one embodiment an interrupt is not issued for a received packet unless a minimum period of time has passed or a minimum number of packets have been received since a previous poll of the network interface or since a previous interrupt was processed.
Each time the network interface is polled, and upon the completion of processing of an interrupt by a host processor, a time counter and/or a packet counter are initialized. Illustratively, the counters are set to programmable threshold values representing, respectively, a maximum period of time that is allowed to pass and a maximum number of packets that may be received before issuing another interrupt. After initialization, the counters begin decrementing toward final programmable values (e.g., zero). As long as polling continues in this embodiment, the counters will be repeatedly re-initialized and will therefore never expire and no interrupts will be generated. In an alternative embodiment, the counters are initialized to initial values and thereafter increment toward threshold values.
In one embodiment of the invention a polling process or software module operating on a host computer polls the network interface by examining a virtual or xe2x80x9caliasxe2x80x9d register that mirrors the network interface""s status register. Such an alias register serves as an alternative path (e.g., address) by which to read the status register. Therefore, when an indicator in the status register changes state to indicate a specific event or condition in the network interface, the corresponding indicator in the alias register also changes. When the network interface is polled, if an indicator in the alias register is set to a state indicating the transfer of a packet, the polling module processes the waiting packet(s). Because the polling module reads the alias register instead of the status register, the alias register is cleared each time the polling module polls the network interface. When the alias register is cleared one or more indicators in the status register may also be cleared, as determined by a programmable mask. Illustratively, the mask comprises a number of entries, each of which corresponds to both an indicator in the status register and a matching indicator in the alias register. The value in each mask entry determines whether an associated status register indicator is cleared when a corresponding alias register indicator is cleared.
In another embodiment of the invention a feedback indicator is added to or associated with the network interface""s status register. The feedback indicator helps avoid an interrupt-claiming problem that may otherwise occur when the polling module clears the status register before an interrupt handler responding to an interrupt can examine the status register and determine why it was called. In particular, when an interrupt is generated because of a status register indicator (other than the feedback indicator) changing state, the feedback indicator is set to a state that indicates an interrupt was generated. Then, although the rest of the status register may be cleared by the polling module by the time the interrupt handler reads the register, the feedback indicator will reveal that a valid interrupt was issued. Without the feedback indicator an error recovery procedure may be initiated, thus hindering the operation of the network interface, if the interrupt handler cannot determine why it was invoked. In this embodiment the polling software may examine the status register directly during each poll, or an alias register may be employed as described above. If an alias register is used, the mask discussed above is configured so that the feedback indicator is not cleared when the alias register is cleared.